By Yoonjin Kim
Coarse-grained reconfigurable structure (CGRA) has emerged as an answer for versatile, application-specific optimization of embedded platforms. supporting you realize the problems fascinated about designing and developing embedded platforms, layout of Low-Power Coarse-Grained Reconfigurable Architectures deals new frameworks for optimizing the structure of elements in embedded structures that allows you to reduce region and store strength. actual program benchmarks and gate-level simulations substantiate those frameworks. the 1st half the e-book explains how you can decrease strength within the configuration cache. The authors current a low-power reconfiguration procedure in line with reusable context pipelining that merges the idea that of context reuse into context pipelining. additionally they suggest dynamic context compression in a position to aiding required bits of the context phrases set to let and the redundant bits set to disable. moreover, they talk about dynamic context administration for decreasing energy intake within the configuration cache via controlling a read/write operation of the redundant context phrases. concentrating on the layout of an economical processing point array to lessen region and gear intake, the second one 1/2 the textual content offers a cheap array textile that uniquely rearranges processing parts and their interconnection designs. The publication additionally describes hierarchical reconfigurable computing arrays which include reconfigurable computing blocks with varieties of verbal exchange constitution. the 2 computing blocks percentage serious assets, supplying an effective verbal exchange interface among them and lowering the general sector. the ultimate bankruptcy takes an built-in method of optimization that pulls at the layout schemes provided in prior chapters. utilizing a case learn, the authors show the synergy influence of mixing a number of layout schemes.
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Each bus operates as two 16-bit data buses. The 16-bit data in the DOR register can be sent to the upper or lower 16 bits of the VBUS or the HBUS. The HBUSs and the VBUSs allow data to be broadcast to the other nano processors in the same row or column. These buses can reduce the communication overhead between processors separated by long distances. The DIR registers accept inputs from the HBUS, the VBUS, the DOR, or the four adjacent nano processors. Because the width of the HBUS and the VBUS is 32 bits, data on the HBUS or the VBUS are stored into a DIR register pair, DIR0 and DIR1, or DIR2 © 2011 by Taylor and Francis Group, LLC Trends in CGRA 17 and DIR3.
In each context block, a context set is associated with a specific row or column of the RC Array. The context word from a context set is broadcast to all eight RCs in the corresponding row (column). Thus, all RCs in a row (column) share a context word and perform the same operation. 6: Organization of context memory. (From H. Singh, “Reconfigurable Architectures for Multimedia and Data-Parallel Application Domains,” Dissertation in University of California, Irvine, University of California, Irvine, 2000.
To guarantee timing, an output register buffers the FUs’ outputs. The multiplexers route data from different sources. The configuration RAM stores a few configurations locally, which can be loaded on a cycle-by-cycle basis. The configurations © 2011 by Taylor and Francis Group, LLC Trends in CGRA 23 can also be loaded from the memory hierarchy, at the cost of extra delay if the local configuration RAM isn’t big enough. Like instructions in microprocessors, the configurations control the basic components’ behavior by selecting operations and controlling multiplexers.
Design of Low-Power Coarse-Grained Reconfigurable Architectures by Yoonjin Kim